.main clear
vlib work
vlog ./*.v
vlog ./device_sim_module/*.v
vlog ./cycloneive_lib/*.v
vlog ../design/*.v
vlog ../ipcore_dir/*.v
vlog ../ipcore_dir/mult_9X9_sync.v
vlog ../ipcore_dir/mult_9X9.v
vlog ../ipcore_dir/sram_1k8i_tdp.v
vlog ../ipcore_dir/sram_1024_8_sdp.v
vlog ../design/sys_reset_ctrl.v

vsim -voptargs=+acc work.testbench_top

add log -r /*

#do wave_cascade.do
#do adj_wr.do
#do sdr.do
#do wave_2color.do
#do test_out.do
#do sync.do
do wave.do
#do sdr_w_r.do
run 3ms
